问题日志

(base) ➜  bin ./vitis_hls -showguiout

****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit)
  **** SW Build 3670227 on Oct 13 2022
  **** IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

source /home/ztn/Embedded/Xilinx/Vitis_HLS/2022.2/scripts/vitis_hls/hls.tcl -notrace
INFO: [HLS 200-10] Running '/home/ztn/Embedded/Xilinx/Vitis_HLS/2022.2/bin/unwrapped/lnx64.o/vitis_hls'
INFO: [HLS 200-10] For user 'ztn' on host 'ztn-Legion-Y9000P-IRX8' (Linux_x86_64 version 6.8.0-49-generic) on Tue Dec 10 15:44:46 CST 2024
INFO: [HLS 200-10] On os Ubuntu 24.04.1 LTS
INFO: [HLS 200-10] In directory '/home/ztn/Embedded/Xilinx/Vitis_HLS/2022.2/bin'
INFO: [HLS 200-10] Bringing up Vitis HLS GUI ... 
HLS_GUI_DEBUG_INFO: Start loading HLS Swig Library: xv_hls_main
HLS_GUI_DEBUG_INFO: Finish loading HLS Swig Library: xv_hls_main
HLS_GUI_DEBUG_INFO: Running GuiDriver.tclInitFromJava, tclIsRunning=false
INFO: [HLS 200-10] Running '/home/ztn/Embedded/Xilinx/Vitis_HLS/2022.2/tps/lnx64/jre11.0.11_9/bin/java'
INFO: [HLS 200-10] For user 'ztn' on host 'ztn-Legion-Y9000P-IRX8' (Linux_x86_64 version 6.8.0-49-generic) on Tue Dec 10 15:44:48 CST 2024
INFO: [HLS 200-10] On os Ubuntu 24.04.1 LTS
INFO: [HLS 200-10] In directory '/home/ztn/Embedded/Xilinx/Vitis_HLS/2022.2/bin'
HLS_GUI_DEBUG_INFO: TCL was started from GUI
HLS_GUI_DEBUG_INFO: Start initializing Parts data
HLS_GUI_DEBUG_INFO: Start initializing Boards data
SLF4J: Failed to load class "org.slf4j.impl.StaticLoggerBinder".
SLF4J: Defaulting to no-operation (NOP) logger implementation
SLF4J: See http://www.slf4j.org/codes.html#StaticLoggerBinder for further details.
(Vitis HLS:66803): Gtk-WARNING **: 15:44:48.936: Could not load a pixbuf from icon theme.
This may indicate that pixbuf loaders or the mime database could not be found.
**
Gtk:ERROR:../../../gtk/gtkiconhelper.c:495:ensure_surface_for_gicon: assertion failed (error == NULL): Failed to load /usr/share/icons/breeze-dark/status/16/image-missing.svg: Unable to load image-loading module: /usr/lib/x86_64-linux-gnu/gdk-pixbuf-2.0/2.10.0/loaders/libpixbufloader-svg.so: /home/ztn/Embedded/Xilinx/Vitis_HLS/2022.2/lib/lnx64.o/Ubuntu/libstdc++.so.6: version `GLIBCXX_3.4.30' not found (required by /lib/x86_64-linux-gnu/libicuuc.so.74) (gdk-pixbuf-error-quark, 5)
Bail out! Gtk:ERROR:../../../gtk/gtkiconhelper.c:495:ensure_surface_for_gicon: assertion failed (error == NULL): Failed to load /usr/share/icons/breeze-dark/status/16/image-missing.svg: Unable to load image-loading module: /usr/lib/x86_64-linux-gnu/gdk-pixbuf-2.0/2.10.0/loaders/libpixbufloader-svg.so: /home/ztn/Embedded/Xilinx/Vitis_HLS/2022.2/lib/lnx64.o/Ubuntu/libstdc++.so.6: version `GLIBCXX_3.4.30' not found (required by /lib/x86_64-linux-gnu/libicuuc.so.74) (gdk-pixbuf-error-quark, 5)
INFO: [HLS 200-112] Total CPU user time: 12.91 seconds. Total CPU system time: 0.74 seconds. Total elapsed time: 4.02 seconds; peak allocated memory: 98.949 MB.
INFO: [Common 17-206] Exiting vitis_hls at Tue Dec 10 15:44:50 2024...
(base) ➜  bin

解决方法,软连接libstdc++.so.6到系统库

(base) ➜  bin cd /home/ztn/Embedded/Xilinx/Vitis_HLS/2022.2/lib/lnx64.o/Ubuntu/               
(base) ➜  Ubuntu ls
18  20  libgcc_s.so.1  libgomp.so.1  libstdc++.so  libstdc++.so.6
(base) ➜  Ubuntu mv libstdc++.so.6 libstdc++.so.6.old
(base) ➜  Ubuntu ls
18  20  libgcc_s.so.1  libgomp.so.1  libstdc++.so  libstdc++.so.6.old
(base) ➜  Ubuntu ln 
(base) ➜  Ubuntu ls -l 
total 1816
drwxr-xr-x  2 ztn ztn    4096 12月  8 23:09 18
drwxr-xr-x  2 ztn ztn    4096 12月  8 23:09 20
-rwxr-xr-x 25 ztn ztn   94000 10月 14  2022 libgcc_s.so.1
-rwxr-xr-x 25 ztn ztn  184304 10月 14  2022 libgomp.so.1
lrwxrwxrwx  1 ztn ztn      14 12月  8 23:09 libstdc++.so -> libstdc++.so.6
-rwxr-xr-x 35 ztn ztn 1570176 10月 14  2022 libstdc++.so.6.old
(base) ➜  Ubuntu ln -s /usr/lib/x86_64-linux-gnu/libstdc++.so.6 libstdc++.so.6     
(base) ➜  Ubuntu ls -l
total 1816
drwxr-xr-x  2 ztn ztn    4096 12月  8 23:09 18
drwxr-xr-x  2 ztn ztn    4096 12月  8 23:09 20
-rwxr-xr-x 25 ztn ztn   94000 10月 14  2022 libgcc_s.so.1
-rwxr-xr-x 25 ztn ztn  184304 10月 14  2022 libgomp.so.1
lrwxrwxrwx  1 ztn ztn      14 12月  8 23:09 libstdc++.so -> libstdc++.so.6
lrwxrwxrwx  1 ztn ztn      40 12月 10 15:46 libstdc++.so.6 -> /usr/lib/x86_64-linux-gnu/libstdc++.so.6
-rwxr-xr-x 35 ztn ztn 1570176 10月 14  2022 libstdc++.so.6.old
(base) ➜  Ubuntu

然后就可以启动

Touhou Resource:https://tieba.baidu.com/p/9007150098

ZYNQ 7010

Boot mode

https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Boot-Mode-Pin-Settings

From zdyz:

Note that can only boot from SD0

Can I boot from SD1 port in Zynq 7000?

Hardware rasterizer

https://www.youtube.com/watch?v=9eydUJl_dRQ, https://github.com/fpgarevolution/FlyingCubes3D/tree/main?tab=readme-ov-file
using PYNQ-Z1(XC7Z020CLG400) Sch

采用flyby拓扑

看了文档PS DDRC支持auto training(write leveling), https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/DRAM-Training
写了`Successful training depends on providing an approximate minimum DQS to CLK delay value. This value should be estimated based on system board layout as well as package delay information.
CK 比DQS长就行，可以看ZYBO的指示，它们CK比DQS短，因此导致了negative CK-to-DQS的error.https://digilent.com/reference/programmable-logic/zybo-z7/reference-manual 关于PS DDRC delay怎么设置可以参考他们的board file
https://www.amobbs.com/thread-5684869-1-1.html 里面说

本帖最后由 dr2001 于 2017-12-15 08:21 编辑
Zynq的DDR3链路训练是自动的，不用人工介入；默认CLK组要比数据组长。
有特殊情况，算好延迟填写好有利于链路训练收敛（或加速收敛）。寄存器可以看链路训练结果，如果链路特殊的话，请查看验证。

DDR3 layout reference

本来是打算自己画的结果太难了,layout有问题，拉线就非常困难
zynq7010/7020核心板众筹openzynq(单片)
sdr5ZYNQ 和 DDR3 的 4 层板（双片四层)

画画心得

1. 先别等长T to src
2. T to src,T to ddr拉完后，设置Spacing8mil规则然后开始修T to ddr(以最长的为target)，不用担心最外面的过孔和线距离不到8mil，后面会修完
3. 两片ddr分开点，中间空多点
4. 中间不够长(横线等长),就往两边借道
5. 如果原来的网络有T点，你原理图加了个R到Vtt，那么记得在改新规则(SigXplorer)后把原来的T点unschedule了(在net schedule里)，不然会变黄，还得把R连好线
6. T点不能是,比如这个板子的odt，三个线同时连R，所以拓扑上没有T点
7. 电源fanout 用8mil
   

   关于pindelay

   最后忘记做pindelay等长了，具体做法:https://www.eet-china.com/mp/a163664.html, https://adaptivesupport.amd.com/s/question/0D52E00006hpkbgSAA/ddr-chip-package-delay?language=en_US
   但我看harbor的板子，clk_n 离最大网络差300mil,加上pindelay(A12,1457-1287 +(579-316)=433mil), 就没管了，反正jlc没有Pindelay功能。以后再说吧，先把final做了，不然周末没完没了了

   Spartan-7 XC7S50

   HDMI

   关于50Ohm 上拉,TMDS电平是3V3的，但看https://community.element14.com/technologies/fpga-group/b/blog/posts/arty-s7---imaging-system-part-3-adding-a-physical-hdmi-port-to-arty-s7 这篇文章感觉不用上拉也行.
   然后HR Bank都支持TMDS IO,只要这个bank用3V3供电，具体参考ug471_7Series_SelectIO.

   Download program to SPI Flash

   包括如何改SPI programming 速率,等等
   一开始load慢是因为SPI x1 + 3Mhz导致的，本质上是修改xdc文件

   set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
   set_property CONFIG_MODE SPIx4 [current_design]
   set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]

   https://www.instructables.com/Flashing-a-MicroBlaze-Program/

   Spartan-MIG7

8. IO管脚定义规则(DQ,ADDR,CMD等) Zynq 7000 SoC and 7 Series Devices Memory Interface Solutions User Guide (UG586)
   

   System clock input

   The system clock input must be in the same column as the memory interface. The system clock input is recommended to be in the address/control bank, when possible.
   Recommended: Although the MIG allows system clock selection to be in different super logic regions (SLRs), it is not recommended due to the additional clock jitter in this topology.

   可以从different SLR(bank) 输入时钟，Narvi 7 Spartan就是这么做的，但是urbana board 在bank35放了一个100mhz差分时钟.
   最好还是放一个在Bank35.
   MIG 7 Series FPGAs DDR3/DDR2 - Clocking Guidelines and43185 - MIG 7 Series - Requirement of System Clock Input 说clk 必须在同一列的bank内
   但是在Vivado: Two Clock Wizard ports with same settings?里面有人说说，只要pass了MIG的customize,任何一个clk都行,甚至从clk wizard.

SPI Nor flash选型

W25Q128 BV FV JV(BV FV都停产了，最新的是JV)
原版用的是MT25QL128，然后spartan 7 支持winbond家的见AMD-Xilinx-UG908的Spartan 7 Configuration Memory Devices

Xilinx Vivado ISE无法启动调试器服务器hw_server

https://zhuanlan.zhihu.com/p/670343325
原因是windows保留了默认端口3121，去掉就行

Xilinx 烧录器参考

FT2232H

1.支持串口的高速Xilinx下载器-FT2232H,自制Xilinx JTAG仿真器
2.参考Urbana Board

FT232H

TT_Digilent_JTAG_HS2
自制Xilinx JTAG仿真器

烧录方法

本质上是烧录到eeprom 93LC56B里面

1. program_ftdi
   基于FT2232集成USB直接实现XilinxJTAG和UART串口
   Programming FTDI Devices for Vivado Hardware Manager Support
   可以无脑烧录FT232H和FT2232H,FT4232H
   2.还有FTDI官方的FT_PROG也可以烧录，还可以保存设置复制到另一个设备上
   视频FT2232HL制作JTAG下载器驱动安装教程
   3.此外针对FT2232H还有Digilent的售后工具:DigilentFTDIConfig.exe

   ch347F

   使用USB转JTAG芯片CH347在Vivado下调试
   xvcd-ch347
   https://github.com/pengwon/ch347-hs-usb-bridge
   https://www.bilibili.com/video/BV1uH4y1j7Py
   WCH在CH347F实现了Xilinx Virtual Cable
   关于Altera的,参考这个https://oshwhub.com/bitshen/usb-blaster