问题日志

(base) ➜  bin ./vitis_hls -showguiout

****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.2 (64-bit)
  **** SW Build 3670227 on Oct 13 2022
  **** IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

source /home/ztn/Embedded/Xilinx/Vitis_HLS/2022.2/scripts/vitis_hls/hls.tcl -notrace
INFO: [HLS 200-10] Running '/home/ztn/Embedded/Xilinx/Vitis_HLS/2022.2/bin/unwrapped/lnx64.o/vitis_hls'
INFO: [HLS 200-10] For user 'ztn' on host 'ztn-Legion-Y9000P-IRX8' (Linux_x86_64 version 6.8.0-49-generic) on Tue Dec 10 15:44:46 CST 2024
INFO: [HLS 200-10] On os Ubuntu 24.04.1 LTS
INFO: [HLS 200-10] In directory '/home/ztn/Embedded/Xilinx/Vitis_HLS/2022.2/bin'
INFO: [HLS 200-10] Bringing up Vitis HLS GUI ... 
HLS_GUI_DEBUG_INFO: Start loading HLS Swig Library: xv_hls_main
HLS_GUI_DEBUG_INFO: Finish loading HLS Swig Library: xv_hls_main
HLS_GUI_DEBUG_INFO: Running GuiDriver.tclInitFromJava, tclIsRunning=false
INFO: [HLS 200-10] Running '/home/ztn/Embedded/Xilinx/Vitis_HLS/2022.2/tps/lnx64/jre11.0.11_9/bin/java'
INFO: [HLS 200-10] For user 'ztn' on host 'ztn-Legion-Y9000P-IRX8' (Linux_x86_64 version 6.8.0-49-generic) on Tue Dec 10 15:44:48 CST 2024
INFO: [HLS 200-10] On os Ubuntu 24.04.1 LTS
INFO: [HLS 200-10] In directory '/home/ztn/Embedded/Xilinx/Vitis_HLS/2022.2/bin'
HLS_GUI_DEBUG_INFO: TCL was started from GUI
HLS_GUI_DEBUG_INFO: Start initializing Parts data
HLS_GUI_DEBUG_INFO: Start initializing Boards data
SLF4J: Failed to load class "org.slf4j.impl.StaticLoggerBinder".
SLF4J: Defaulting to no-operation (NOP) logger implementation
SLF4J: See http://www.slf4j.org/codes.html#StaticLoggerBinder for further details.
(Vitis HLS:66803): Gtk-WARNING **: 15:44:48.936: Could not load a pixbuf from icon theme.
This may indicate that pixbuf loaders or the mime database could not be found.
**
Gtk:ERROR:../../../gtk/gtkiconhelper.c:495:ensure_surface_for_gicon: assertion failed (error == NULL): Failed to load /usr/share/icons/breeze-dark/status/16/image-missing.svg: Unable to load image-loading module: /usr/lib/x86_64-linux-gnu/gdk-pixbuf-2.0/2.10.0/loaders/libpixbufloader-svg.so: /home/ztn/Embedded/Xilinx/Vitis_HLS/2022.2/lib/lnx64.o/Ubuntu/libstdc++.so.6: version `GLIBCXX_3.4.30' not found (required by /lib/x86_64-linux-gnu/libicuuc.so.74) (gdk-pixbuf-error-quark, 5)
Bail out! Gtk:ERROR:../../../gtk/gtkiconhelper.c:495:ensure_surface_for_gicon: assertion failed (error == NULL): Failed to load /usr/share/icons/breeze-dark/status/16/image-missing.svg: Unable to load image-loading module: /usr/lib/x86_64-linux-gnu/gdk-pixbuf-2.0/2.10.0/loaders/libpixbufloader-svg.so: /home/ztn/Embedded/Xilinx/Vitis_HLS/2022.2/lib/lnx64.o/Ubuntu/libstdc++.so.6: version `GLIBCXX_3.4.30' not found (required by /lib/x86_64-linux-gnu/libicuuc.so.74) (gdk-pixbuf-error-quark, 5)
INFO: [HLS 200-112] Total CPU user time: 12.91 seconds. Total CPU system time: 0.74 seconds. Total elapsed time: 4.02 seconds; peak allocated memory: 98.949 MB.
INFO: [Common 17-206] Exiting vitis_hls at Tue Dec 10 15:44:50 2024...
(base) ➜  bin

解决方法,软连接libstdc++.so.6到系统库

(base) ➜  bin cd /home/ztn/Embedded/Xilinx/Vitis_HLS/2022.2/lib/lnx64.o/Ubuntu/               
(base) ➜  Ubuntu ls
18  20  libgcc_s.so.1  libgomp.so.1  libstdc++.so  libstdc++.so.6
(base) ➜  Ubuntu mv libstdc++.so.6 libstdc++.so.6.old
(base) ➜  Ubuntu ls
18  20  libgcc_s.so.1  libgomp.so.1  libstdc++.so  libstdc++.so.6.old
(base) ➜  Ubuntu ln 
(base) ➜  Ubuntu ls -l 
total 1816
drwxr-xr-x  2 ztn ztn    4096 12月  8 23:09 18
drwxr-xr-x  2 ztn ztn    4096 12月  8 23:09 20
-rwxr-xr-x 25 ztn ztn   94000 10月 14  2022 libgcc_s.so.1
-rwxr-xr-x 25 ztn ztn  184304 10月 14  2022 libgomp.so.1
lrwxrwxrwx  1 ztn ztn      14 12月  8 23:09 libstdc++.so -> libstdc++.so.6
-rwxr-xr-x 35 ztn ztn 1570176 10月 14  2022 libstdc++.so.6.old
(base) ➜  Ubuntu ln -s /usr/lib/x86_64-linux-gnu/libstdc++.so.6 libstdc++.so.6     
(base) ➜  Ubuntu ls -l
total 1816
drwxr-xr-x  2 ztn ztn    4096 12月  8 23:09 18
drwxr-xr-x  2 ztn ztn    4096 12月  8 23:09 20
-rwxr-xr-x 25 ztn ztn   94000 10月 14  2022 libgcc_s.so.1
-rwxr-xr-x 25 ztn ztn  184304 10月 14  2022 libgomp.so.1
lrwxrwxrwx  1 ztn ztn      14 12月  8 23:09 libstdc++.so -> libstdc++.so.6
lrwxrwxrwx  1 ztn ztn      40 12月 10 15:46 libstdc++.so.6 -> /usr/lib/x86_64-linux-gnu/libstdc++.so.6
-rwxr-xr-x 35 ztn ztn 1570176 10月 14  2022 libstdc++.so.6.old
(base) ➜  Ubuntu

然后就可以启动

Touhou Resource:https://tieba.baidu.com/p/9007150098

Context Switch

ra(x1) saved by _swtch,
And _swtch should act like an 'nop'
And tp is never used by compiler

On Msys2 MINGW64

cf. https://wiki.qemu.org/Hosts/W32

pacman -S mingw-w64-x86_64-gcc mingw-w64-x86_64-glib2 mingw-w64-x86_64-gettext-runtime mingw-w64-x86_64-gcc mingw-w64-x86_64-binutils mingw-w64-x86_64-pixman mingw-w64-x86_64-SDL2 mingw-w64-x86_64-gtk3 mingw-w64-x86_64-riscv64-unknown-elf-gcc mingw-w64-x86_64-gdb-multiarch git diffutils zsh vim)

Please enable Developer Mode to support soft link without Administrator permission, otherwise it prompts

Found ninja-1.12.1 at D:/msys64/usr/bin/ninja.exe
Running postconf script 'D:/ZJUI/ECE391/qemu/build/pyvenv/bin/python3.exe D:/ZJUI/ECE391/qemu/scripts/symlink-install-tree.py'
Please enable Developer Mode to support soft link without Administrator permission
error making symbolic link D:/msys64/opt/toolchains/riscv/lib/libfdt.a
Traceback (most recent call last):
  File "D:/ZJUI/ECE391/qemu/scripts/symlink-install-tree.py", line 35, in <module>
    raise e
  File "D:/ZJUI/ECE391/qemu/scripts/symlink-install-tree.py", line 28, in <module>
    os.symlink(source, bundle_dest)
OSError: [WinError 1314] 客户端没有所需的特权。: 'D:/ZJUI/ECE391/qemu/build/subprojects/dtc/libfdt/libfdt.a' -> 'qemu-bundle/msys64/opt/toolchains/riscv/lib/libfdt.a'

./configure --prefix=/opt/toolchains/riscv --target-list=riscv32-softmmu,riscv64-softmmu --enable-gtk --enable-system --disable-werror
make -j
make install

Change zsh for MINGW session https://superuser.com/questions/961699/change-default-shell-on-msys2

sh -c "$(curl -fsSL https://raw.githubusercontent.com/ohmyzsh/ohmyzsh/master/tools/install.sh)"

Set in mingw64.ini:

SHELL=/usr/bin/zsh

There is no PTS on windows so use telnet instead
source:https://www.uni-koeln.de/~pbogusze/posts/QEMU_serial_console.html

qemu-system-riscv64 -machine virt -bios none -kernel cp1.elf -m 8M -nographic -serial mon:stdio -serial telnet:localhost:4321,server,nowait

Add D:\msys64\mingw64\bin to PATH of Windows
Then telnet to attach to con1

telnet localhost 4321

Some Programming/Reference Manuals

• Volume 1, Unprivileged Specification version 20240411 PDF GitHub
• Volume 2, Privileged Specification version 20240411 PDF GitHub
• PLIC Specs v1.0.0
  For newest PLIC manual please refer to https://riscv.org/technical/specifications/ and https://github.com/riscv/riscv-plic-spec/releases
• NS16550 UART(Texus Instrument)
  cf. Section 8.6 for register specification.

  Note on CSR instructions

  CSR can't be accessed directly, thus those instructions are needed.
  Only 6 instructions, CSR[RS,RC,RW,RSI,RCI,RWI],I is immediate.
  S for set, C for clear, W for write, other mnemonic(e.g. CSRR/CSRW) are pseudo-instructions with either rs1=x0 or ds=x0.
  For both CSRRS and CSRRC, if rs1=x0, then the instruction will not write to the CSR at all
  For both CSRRSI and CSRRCI, if uimm[4:0] field is zero, then the instruction will not write to the CSR at all
  But CAVEAT LECTOR!, if rs1=x0 or uimm[4:0]=0 for CSRRW or CSRRWI, then csr will be CLEARED

  IRQ number(PLIC source no./id) and MMAP(Memory Mapping) in ECE391 FA24

  It is modified based on https://github.com/qemu/qemu/blob/master/hw/riscv/virt.c
  7 uarts are added and IRQ number of RTC is moved to 9
  
  

  Ext ASM in C code

  Reference How to Use Inline Assembly Language in C Code

• Do not expect a sequence of asm statements to remain perfectly consecutive after compilation, even when you are using the volatile qualifier. If certain instructions need to remain consecutive in the output, put them in a single multi-instruction asm statement.
• \n\t to seperate assembly instructions in a single Assembly Template
  Input: using , delimiter

  [ [asmSymbolicName] ] constraint (cexpression)

  Output:

  [ [asmSymbolicName] ] constraint (cvariablename)

• asmSymbolicName
  Specifies a symbolic name for the operand. Reference the name in the assembler template by enclosing it in square brackets (i.e. %[Value]). The scope of the name is the asm statement that contains the definition. Any valid C variable name is acceptable, including names already defined in the surrounding code. No two operands within the same asm statement can use the same symbolic name.
  When not using an asmSymbolicName, use the (zero-based) position of the operand in the list of operands in the assembler template. For example if there are two output operands and three inputs, use %2 in the template to refer to the first input operand, %3 for the second, and %4 for the third.

For example

uint32_t Mask = 1234;
uint32_t Index;
asm ("bsfl %[aMask], %[aIndex]"
     : [aIndex] "=r" (Index)
     : [aMask] "r" (Mask)
     : "cc");

if no asmSymbolicName

__asm__ ("btsl %2,%1\n\t" // Turn on zero-based bit #Offset in Base.
         "sbb %0,%0"      // Use the CF to calculate old.
   : "=r" (old), "+rm" (*Base)
   : "Ir" (Offset)
   : "cc");
return old;

output registers begin with 0, the number of input regs are after output regs.

If using I(immediate) as constraint, the input value must be known at assembly time or later.

Control Status Registers(CSR)

mstatus:
mip:
mie:
mtvec:
mcause:
mepc:

PLIC

Each source has a priority(0 is disabled, higher for high prio).
destination is a contex, which is a HART combined with mode(M/S)
every context (e.g. context 0) has a source enable(not prio).
PLIC Indicates which interrupt source raised the interrupt by

Trap entry

• Places current PC into mepc CSR
• Sets mstatus.MPP to previous privilege mode (current privilege mode is decided by path)
• Sets mstatus.MPIE to mstatus.MIE
• Sets mstatus.MIE to 0 (interrupts disabled on entry)
• Sets PC to mtvec.BASE (if mode 0) or mtvec.BASE + 4×cause
  

  Trap exit

• Sets mstatus.mie to mstatus.MPP ; sets MPIE to 1
• Changes privilege mode to mstatus.MPP; sets MPP to 0
• Set PC to mepc
  You will get to the vector addr of Externel M-Mode Interrupt(mtvec[1:0]==2b'01) or just BASE(mtvec[1:0]==2b'00), then check which source issued the interrupt, then go to the corresponding ISR(interrupt service routine) or what so-called interrupt handler.
  A CPU claims the interrupt to identify source
• CPU reads special per-context claim register on PLIC
• PLIC returns highest priority source number on read
• PLIC will not offer the interrupt source to other CPUs
• CPU has committed to servicing it
  CPU can always read claim register to poll for highest priority interrupt

  End procedure for PLIC(Interrupt Completion)

  When CPU is finished servicing the itnerrupt, it signals completion to the PLIC

• CPU writes source number to its claim register on PLIC
• This indicates CPU is done servicing the interrupt source