Some Programming/Reference Manuals

• Volume 1, Unprivileged Specification version 20240411 PDF GitHub
• Volume 2, Privileged Specification version 20240411 PDF GitHub
• PLIC Specs v1.0.0
  For newest PLIC manual please refer to https://riscv.org/technical/specifications/ and https://github.com/riscv/riscv-plic-spec/releases
• NS16550 UART(Texus Instrument)
  cf. Section 8.6 for register specification.

  Note on CSR instructions

  CSR can't be accessed directly, thus those instructions are needed.
  Only 6 instructions, CSR[RS,RC,RW,RSI,RCI,RWI],I is immediate.
  S for set, C for clear, W for write, other mnemonic(e.g. CSRR/CSRW) are pseudo-instructions with either rs1=x0 or ds=x0.
  For both CSRRS and CSRRC, if rs1=x0, then the instruction will not write to the CSR at all
  For both CSRRSI and CSRRCI, if uimm[4:0] field is zero, then the instruction will not write to the CSR at all
  But CAVEAT LECTOR!, if rs1=x0 or uimm[4:0]=0 for CSRRW or CSRRWI, then csr will be CLEARED

  IRQ number(PLIC source no./id) and MMAP(Memory Mapping) in ECE391 FA24

  It is modified based on https://github.com/qemu/qemu/blob/master/hw/riscv/virt.c
  7 uarts are added and IRQ number of RTC is moved to 9
  
  

  Ext ASM in C code

  Reference How to Use Inline Assembly Language in C Code

• Do not expect a sequence of asm statements to remain perfectly consecutive after compilation, even when you are using the volatile qualifier. If certain instructions need to remain consecutive in the output, put them in a single multi-instruction asm statement.
• \n\t to seperate assembly instructions in a single Assembly Template
  Input: using , delimiter

  [ [asmSymbolicName] ] constraint (cexpression)

  Output:

  [ [asmSymbolicName] ] constraint (cvariablename)

• asmSymbolicName
  Specifies a symbolic name for the operand. Reference the name in the assembler template by enclosing it in square brackets (i.e. %[Value]). The scope of the name is the asm statement that contains the definition. Any valid C variable name is acceptable, including names already defined in the surrounding code. No two operands within the same asm statement can use the same symbolic name.
  When not using an asmSymbolicName, use the (zero-based) position of the operand in the list of operands in the assembler template. For example if there are two output operands and three inputs, use %2 in the template to refer to the first input operand, %3 for the second, and %4 for the third.

For example

uint32_t Mask = 1234;
uint32_t Index;
asm ("bsfl %[aMask], %[aIndex]"
     : [aIndex] "=r" (Index)
     : [aMask] "r" (Mask)
     : "cc");

if no asmSymbolicName

__asm__ ("btsl %2,%1\n\t" // Turn on zero-based bit #Offset in Base.
         "sbb %0,%0"      // Use the CF to calculate old.
   : "=r" (old), "+rm" (*Base)
   : "Ir" (Offset)
   : "cc");
return old;

output registers begin with 0, the number of input regs are after output regs.

If using I(immediate) as constraint, the input value must be known at assembly time or later.

Control Status Registers(CSR)

mstatus:
mip:
mie:
mtvec:
mcause:
mepc:

PLIC

Each source has a priority(0 is disabled, higher for high prio).
destination is a contex, which is a HART combined with mode(M/S)
every context (e.g. context 0) has a source enable(not prio).
PLIC Indicates which interrupt source raised the interrupt by

Trap entry

• Places current PC into mepc CSR
• Sets mstatus.MPP to previous privilege mode (current privilege mode is decided by path)
• Sets mstatus.MPIE to mstatus.MIE
• Sets mstatus.MIE to 0 (interrupts disabled on entry)
• Sets PC to mtvec.BASE (if mode 0) or mtvec.BASE + 4×cause
  

  Trap exit

• Sets mstatus.mie to mstatus.MPP ; sets MPIE to 1
• Changes privilege mode to mstatus.MPP; sets MPP to 0
• Set PC to mepc
  You will get to the vector addr of Externel M-Mode Interrupt(mtvec[1:0]==2b'01) or just BASE(mtvec[1:0]==2b'00), then check which source issued the interrupt, then go to the corresponding ISR(interrupt service routine) or what so-called interrupt handler.
  A CPU claims the interrupt to identify source
• CPU reads special per-context claim register on PLIC
• PLIC returns highest priority source number on read
• PLIC will not offer the interrupt source to other CPUs
• CPU has committed to servicing it
  CPU can always read claim register to poll for highest priority interrupt

  End procedure for PLIC(Interrupt Completion)

  When CPU is finished servicing the itnerrupt, it signals completion to the PLIC

• CPU writes source number to its claim register on PLIC
• This indicates CPU is done servicing the interrupt source

vscode 前置

1. 安装C/C++插件
   
2. 开启Allow Breakpoints Everywhere Vscode 在汇编文件中添加调试断点
   
3. Makefile中添加ASFLAGS = -g
   

   vscode文件设置

   在workspace下.vscode下新建启动文件与任务文件launch.json, tasks.json

   launch.json

   在miDebuggerPath 填riscv-gdb绝对路径，program填要调的程序

   {
   // Use IntelliSense to learn about possible attributes.
   // Hover to view descriptions of existing attributes.
   // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387
   "version": "0.2.0",
   "configurations": [
       {
           "name": "Debug RISC-V",
           "type": "cppdbg",
           "request": "launch",
           "program":"${workspaceFolder}/demo.elf",
           "cwd": "${workspaceFolder}",
           "miDebuggerPath": "/opt/toolchains/riscv/bin/riscv64-unknown-elf-gdb",
           "miDebuggerServerAddress": "localhost:1234",
           "stopOnEntry": true,
           "preLaunchTask": "Run QEMU"
       }
   ]
   }

   tasks.json

在command中修改调试器启动参数，修改对应启动elf文件。不要删除前面的一条命令echo 'QEMU started'，这个是为了让vscode结束启动等待用

{
    // See https://go.microsoft.com/fwlink/?LinkId=733558
    // for the documentation about the tasks.json format
    "version": "2.0.0",
    "tasks": [
        {
            "label": "Build",
            "type": "shell",
            "command": "make",
            "args": [
                ""
            ],
            "group": {
                "kind": "build",
                "isDefault": true
            },
            "problemMatcher": [
                "$gcc"
            ]
        },
        {
            "label": "Run QEMU",
            "type": "shell",
            "command": "echo 'QEMU started';qemu-system-riscv64 -s -S -machine virt -bios none -kernel demo.elf -m 128M -serial mon:stdio -device bochs-display",
            "dependsOn": ["Build"],
            "args": [],
            "group": {
                "kind": "test",
                "isDefault": true
            },
            "isBackground": true,
            "problemMatcher": [
                {
                    "pattern": [
                        {
                            "regexp": ".",
                            "file": 1,
                            "location": 2,
                            "message": 3
                        }
                    ],
                    "background": {
                        "activeOnStart": true,
                        "beginsPattern": ".",
                        "endsPattern": ".",
                    }
                }
            ]
        }
    ]
}

ZYNQ 7010

Boot mode

https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Boot-Mode-Pin-Settings

From zdyz:

Note that can only boot from SD0

Can I boot from SD1 port in Zynq 7000?

Hardware rasterizer

https://www.youtube.com/watch?v=9eydUJl_dRQ, https://github.com/fpgarevolution/FlyingCubes3D/tree/main?tab=readme-ov-file
using PYNQ-Z1(XC7Z020CLG400) Sch

采用flyby拓扑

看了文档PS DDRC支持auto training(write leveling), https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/DRAM-Training
写了`Successful training depends on providing an approximate minimum DQS to CLK delay value. This value should be estimated based on system board layout as well as package delay information.
CK 比DQS长就行，可以看ZYBO的指示，它们CK比DQS短，因此导致了negative CK-to-DQS的error.https://digilent.com/reference/programmable-logic/zybo-z7/reference-manual 关于PS DDRC delay怎么设置可以参考他们的board file
https://www.amobbs.com/thread-5684869-1-1.html 里面说

本帖最后由 dr2001 于 2017-12-15 08:21 编辑
Zynq的DDR3链路训练是自动的，不用人工介入；默认CLK组要比数据组长。
有特殊情况，算好延迟填写好有利于链路训练收敛（或加速收敛）。寄存器可以看链路训练结果，如果链路特殊的话，请查看验证。

DDR3 layout reference

本来是打算自己画的结果太难了,layout有问题，拉线就非常困难
zynq7010/7020核心板众筹openzynq(单片)
sdr5ZYNQ 和 DDR3 的 4 层板（双片四层)

画画心得

1. 先别等长T to src
2. T to src,T to ddr拉完后，设置Spacing8mil规则然后开始修T to ddr(以最长的为target)，不用担心最外面的过孔和线距离不到8mil，后面会修完
3. 两片ddr分开点，中间空多点
4. 中间不够长(横线等长),就往两边借道
5. 如果原来的网络有T点，你原理图加了个R到Vtt，那么记得在改新规则(SigXplorer)后把原来的T点unschedule了(在net schedule里)，不然会变黄，还得把R连好线
6. T点不能是,比如这个板子的odt，三个线同时连R，所以拓扑上没有T点
7. 电源fanout 用8mil
   

   关于pindelay

   最后忘记做pindelay等长了，具体做法:https://www.eet-china.com/mp/a163664.html, https://adaptivesupport.amd.com/s/question/0D52E00006hpkbgSAA/ddr-chip-package-delay?language=en_US
   但我看harbor的板子，clk_n 离最大网络差300mil,加上pindelay(A12,1457-1287 +(579-316)=433mil), 就没管了，反正jlc没有Pindelay功能。以后再说吧，先把final做了，不然周末没完没了了

   Spartan-7 XC7S50

   HDMI

   关于50Ohm 上拉,TMDS电平是3V3的，但看https://community.element14.com/technologies/fpga-group/b/blog/posts/arty-s7---imaging-system-part-3-adding-a-physical-hdmi-port-to-arty-s7 这篇文章感觉不用上拉也行.
   然后HR Bank都支持TMDS IO,只要这个bank用3V3供电，具体参考ug471_7Series_SelectIO.

   Download program to SPI Flash

   包括如何改SPI programming 速率,等等
   一开始load慢是因为SPI x1 + 3Mhz导致的，本质上是修改xdc文件

   set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
   set_property CONFIG_MODE SPIx4 [current_design]
   set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]

   https://www.instructables.com/Flashing-a-MicroBlaze-Program/

   Spartan-MIG7

8. IO管脚定义规则(DQ,ADDR,CMD等) Zynq 7000 SoC and 7 Series Devices Memory Interface Solutions User Guide (UG586)
   

   System clock input

   The system clock input must be in the same column as the memory interface. The system clock input is recommended to be in the address/control bank, when possible.
   Recommended: Although the MIG allows system clock selection to be in different super logic regions (SLRs), it is not recommended due to the additional clock jitter in this topology.

   可以从different SLR(bank) 输入时钟，Narvi 7 Spartan就是这么做的，但是urbana board 在bank35放了一个100mhz差分时钟.
   最好还是放一个在Bank35.
   MIG 7 Series FPGAs DDR3/DDR2 - Clocking Guidelines and43185 - MIG 7 Series - Requirement of System Clock Input 说clk 必须在同一列的bank内
   但是在Vivado: Two Clock Wizard ports with same settings?里面有人说说，只要pass了MIG的customize,任何一个clk都行,甚至从clk wizard.

SPI Nor flash选型

W25Q128 BV FV JV(BV FV都停产了，最新的是JV)
原版用的是MT25QL128，然后spartan 7 支持winbond家的见AMD-Xilinx-UG908的Spartan 7 Configuration Memory Devices

Xilinx Vivado ISE无法启动调试器服务器hw_server

https://zhuanlan.zhihu.com/p/670343325
原因是windows保留了默认端口3121，去掉就行

Xilinx 烧录器参考

FT2232H

1.支持串口的高速Xilinx下载器-FT2232H,自制Xilinx JTAG仿真器
2.参考Urbana Board

FT232H

TT_Digilent_JTAG_HS2
自制Xilinx JTAG仿真器

烧录方法

本质上是烧录到eeprom 93LC56B里面

1. program_ftdi
   基于FT2232集成USB直接实现XilinxJTAG和UART串口
   Programming FTDI Devices for Vivado Hardware Manager Support
   可以无脑烧录FT232H和FT2232H,FT4232H
   2.还有FTDI官方的FT_PROG也可以烧录，还可以保存设置复制到另一个设备上
   视频FT2232HL制作JTAG下载器驱动安装教程
   3.此外针对FT2232H还有Digilent的售后工具:DigilentFTDIConfig.exe

   ch347F

   使用USB转JTAG芯片CH347在Vivado下调试
   xvcd-ch347
   https://github.com/pengwon/ch347-hs-usb-bridge
   https://www.bilibili.com/video/BV1uH4y1j7Py
   WCH在CH347F实现了Xilinx Virtual Cable
   关于Altera的,参考这个https://oshwhub.com/bitshen/usb-blaster